How UR20 Modbus TCP addressing works (read me)
The UR20-FBC-MOD-TCP-V2 fieldbus coupler builds two packed process images from the modules on the rail, in physical left-to-right order:
- Process input image (module → PLC): 16-bit registers starting at
0x0000, read with FC04 (Read Input Registers) or FC03. Digital inputs are also exposed as discrete inputs (FC02) at bit addresses. - Process output image (PLC → module): 16-bit registers starting at
0x0800(2048), read with FC03, written with FC06/FC16. Digital outputs are also exposed as coils (FC01/FC05/FC15).
Layout model: each analog channel takes one 16-bit word. Digital modules are byte-aligned (each starts on a byte boundary; bit lanes 0 or 8 of a register). A point's coil / discrete-input address equals its bit offset within the packed image; its register address is base + (bitOffset ÷ 16).
Authoritative offsets: for mixed digital+analog racks the coupler computes the exact per-module offsets at runtime — read them live from the module-offset table at register 0x2B00. This tool reproduces the standard aligned model, which matches typical racks; modules marked ⚠ have widths that vary by configuration (counters, IO-Link, serial) — confirm against the module manual or 0x2B00.
Other useful coupler registers: coupler ID 0x1000, process output length 0x1010, process input length 0x1011, module parameters 0xC000.